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PD01

Physical Design

Physical design implementation of Block/Top, feasibility analysis, floor plan, power plan, CTS, Routing challenges, STA and LEC challenges at deep micron effects.

  • Minimum 5+ industry experience
  • Should worked on multiple block closures (RTL to GDSII)
  • Worked on leading industry tools (Synopsys/Cadence)
  • Good understanding of LEC
  • Good understanding of layout verification at 14nm/10nm of leading foundries
  • Scripting is plus
  • Positons: Sr.Engg/Lead Engg/Technical Manager
  • Location: Bangalore

Send your profile : hr@thinsil.com

VE02

Verification

System level/Block level verification with methodology driven flows either with UVM/OVM and understanding different protocals.

  • Minimum 4+ industry experience
  • Should worked on system level/Block Level
  • Worked on building verification environment with UVM
  • Coverage analysis
  • Positons: Sr.Engg/Lead Engg/Technical Manager
  • Location: Bangalore

Send your profile : hr@thinsil.com

OT03

Other requirement

There is always a room for right cadidate in following with 5+ years of experience

  • RTL Design
  • Synthesis & STA
  • DFT
  • Layout Verification
  • Logic Equivalance check (LEC)
  • Analog design & Verification
  • Memory Design & Charactarization
  • Std Cell Design & Charactarization

Send your profile : hr@thinsil.com